As integrated circuit technology continues to advance, system-level designers are finding that in many cases they can implement most or all of particular system on a single integrated circuit. For example, numerous different functional blocks along with peripherals formerly attached to a processor at the card level are integrated onto the same die as the processor. Thus, a great deal of effort has been put into the development of system-on-chip (SoC) design methodologies, architectures, design tools, and fabrication techniques. Since SoCs are integrated circuits that combine the major functional elements of a complete end-product into a single chip using intellectual property (IP) blocks, they enable products with a broad and growing diversity of applications (e.g., communication networks, storage networks, set-top boxes, games, embedded devices, etc.) to be realized with higher performance and lower cost.
Many SoC solutions used in applications today are designed as custom integrated circuits, each with its own internal architecture and perhaps specialized software. Logical units within such an integrated circuit are often difficult to extract and reuse in different applications. Consequently, the same function is often redesigned from one application to the next. Consequently, to promote efficient SoC design and reuse, a variety of strategies are used. Since a typical SoC contains numerous functional blocks representing a very large number of logic gates, such designs can be realized through a macro-based approach targeting one or more specific hardware platforms, e.g., specific field programmable gate arrays (FPGAs), or specialized IP core libraries designed to be easily implemented in existing semiconductor fabrication processes. Macro-based design provides numerous benefits during logic entry and verification, and greatly facilitates IP reuse. From generic I/O ports to complex memory controllers and processor cores, each SoC typically uses many of these common macros.
While SoC design offers many advantages, there are still the familiar challenges of designing a complex system, now on a chip. For example, because of increasing design complexity, system architects are often encouraged to explore more and more of their system's performance and behavior in system-level modeling environments. The fidelity of the data obtained from simulating a model depends on the degree of accuracy to which it was modeled. Typically, designers must trade off the extra effort required to create a detailed (low level of abstraction) model and also the extra computational effort required to simulate the detailed model against the level of fidelity in the performance data recovered from it.
Consequently, it is common in the system level design community to suggest creating multiple models of the same system. The system architect selects which aspects of the system to emphasize and can use different formalisms to capture the system model in simulatable form more quickly. Generally speaking, any single model will operate at a single, predefined level of detail. Hybrid models that combine elements of the system described at different levels of detail have been proposed, but once the levels of detail have been selected, they remain fixed for at least the runtime of the model and, commonly, for the duration of the model's existence.
Accordingly, it is desirable to have integrated circuit modeling tools and techniques, and particularly system level modeling tools and techniques, that allow users the flexibility to vary the level of detail for various model components during simulation.